1. Field of the Invention
The present invention relates to an active matrix substrate usable in, for example, a liquid crystal display device.
2. Description of the Related Art
FIG. 9 is a partial equivalent circuit diagram of a conventional active matrix substrate 500.
The active matrix substrate 500 shown in FIG. 9 includes a transparent insulative plate 101 formed of glass or the like, a plurality of gate signal lines 102 formed of tantalum or the like, a plurality of storage capacitance common lines 103 for forming a storage capacitance Cs, and a plurality of source signal lines 104. The gate signal lines 102, the storage capacitance common lines 103 and the source signal lines 104 are provided on the transparent insulative plate 101. The source signal lines 104 are arranged perpendicular to the gate signal lines 102 and the storage capacitance common lines 103. The source signal lines 104 have a two-layer structure including a metal layer and an ITO (indium tin oxide) layer. The active matrix substrate 500 further includes a plurality of pixel electrodes 105 arranged in a matrix and a plurality of thin film transistors (hereinafter, referred to as a "TFT") 106 acting as switching elements. The pixel electrodes 105 are connected to the gate signal lines 102 and the source signal lines 104 through the TFTs 106. In the case where the active matrix substrate 500 is included in a transmissive device, the pixel electrodes 105 are formed of a transparent conductive material such as, for example, ITO. In the case where the active matrix substrate 500 is included in a reflective device, the pixel electrodes 105 are formed of aluminum or the like.
The active matrix substrate 500 further includes, in a peripheral area thereof, gate signal line terminals 107 for inputting synchronization signals, storage capacitance common line terminals 108, and source signal line terminals 109 for inputting video signals. Although not shown in FIG. 9, the terminals 107, 108 and 109 include a transparent conductive layer for covering an underlying metal layer for the purpose of preventing the underlying metal layer from being oxidized. The transparent conductive layer is formed of, for example, ITO, which is used for forming the pixel electrodes 105 and the source signal lines 104.
FIG. 10 is a plan view of one pixel area of the active matrix substrate 500 shown in FIG. 9, from which an interlayer insulative layer and the pixel electrode 105 are omitted for clarity. FIG. 11 is a plan view of one pixel area of the active matrix substrate 500 shown in FIG. 9. FIG. 12 is a cross-sectional view of the one pixel area shown in FIG. 11 taken along line XII--XII in FIG. 11. FIG. 13 is a cross-sectional view of a part of the one pixel area shown in FIG. 11 taken along line XIII--XIII in FIG. 11. As shown in FIG. 11, a peripheral area of the pixel electrode 105 overlaps the gate signal lines 102 and the source signal lines 104. In FIG. 13, an interlayer insulative layer and the pixel electrode 105 are omitted for clarity. The following description will be provided regarding one pixel area for simplicity.
Referring to FIGS. 12 and 13, the gate signal line 102 including a gate electrode 116 and a storage capacitance common line 103 are provided on the transparent insulative plate 101. A gate insulating layer 112 is provided on the transparent insulative plate 101 so as to cover the gate signal line 102 including the gate electrode 116 and the storage capacitance common line 103.
As shown in FIG. 13, a semiconductor layer 113 is provided on the gate insulating layer 112 so as to overlap the gate electrode 116. An n.sup.+ silicon layer 114 and an n.sup.+ silicon layer 115 are provided on the semiconductor layer 113 with a gap interposed therebetween. A source electrode 117 and a drain electrode 110, each formed of an ITO layer 126 and a metal layer 125, are provided on the n.sup.+ silicon layers 115 and 114, respectively. The TFT 106 includes the gate electrode 116, the semiconductor layer 113, the n.sup.+ silicon layers 114 and 115, the source electrode 117 and the drain electrode 110. The gap between the n.sup.+ silicon layers 114 and 115 corresponds to a channel region of the TFT 106.
As best shown in FIG. 11, the ITO layer which is a part of the drain electrode 110 is extended in a direction perpendicular to the gate signal line 102 and the storage capacitance common line 103 and then further extended in a direction overlapping the storage capacitance common line 103. The extended part of the ITO layer acts as a connecting electrode 127. The part of the connecting electrode 127 which overlaps the storage capacitance common line 103 acts as a storage capacitor electrode 127a.
As shown in FIG. 12, the interlayer insulative layer 118 is provided on the gate insulative layer 112 so as to cover the elements provided on the gate insulative layer 112. The pixel electrode 105 is provided on the interlayer insulative layer 118. The interlayer insulative layer 118 has a contact hole 111 provided therethrough. The connecting electrode 127 is electrically connected to the pixel electrode 105 through the contact hole 111. The drain electrode 110 (FIG. 13) is electrically connected to the pixel electrode 105 through the connecting electrode 127. A portion where the storage capacitor electrode 127a, the gate insulative layer 112 and the storage capacitance common line 103 overlap one another acts as a storage capacitor.
In the above-described structure, the pixel electrode 105 overlaps the source signal line 104 due to the interlayer insulative layer 118 provided therebetween. Accordingly, the aperture ratio is raised, and the leak between the source signal line 104 and the pixel electrode 105 is reduced.
A method for producing the conventional active matrix substrate 500 will be described with reference to FIGS. 14A through 14E and 15A through 15E.
FIGS. 14A through 14E are cross-sectional views illustrating a process for producing the TFT 106. FIGS. 15A through 15E are cross-sectional views illustrating a process for producing the gate signal line terminal 107 and the storage capacitance common line terminal 108. Since the terminals 107 and 108 have a substantially identical structure, the gate signal line terminal 107 will be described as an example.
First, as shown in FIGS. 14A and 15A, a metal layer is formed on the transparent insulative plate 101 and patterned into the gate signal lines 102 including the gate electrode 116.
As shown in FIGS. 14B and 15B, the gate insulative layer 112 is formed on the transparent insulative plate 101 so as to cover the gate electrode 116 and the gate signal line 102. Then, as shown in FIG. 14B, the semiconductor layer 113 and an n.sup.+ silicon layer 124 are formed sequentially on the gate insulative layer 112.
As shown in FIG. 15C, a contact hole 112a for forming a connecting portion (represented by reference numeral 130 in FIG. 15D) of the gate signal line terminal 7 is formed in the gate insulative layer 112.
As shown in FIG. 14C, the ITO layer 126 and the metal layer 125 are formed on the n.sup.+ silicon layer 124. The ITO metal layer 125 and the ITO layer 126 are separately patterned by photolithography or the like in this order. As a result, the source electrode 117 and the drain electrode 110 are formed as shown in FIG. 14D, and the connecting portion 130 is formed of the ITO layer 126 which is formed as shown in FIG. 15D as a result of the removal of the metal layer 125. As best shown in FIG. 13, the ITO layer 126 is patterned to extend on the gate insulative layer 112 from the drain electrode 110 in a direction perpendicular to the gate signal line 102 (FIG. 11) and then in a direction overlapping the storage capacitance common line 103 so as to act as the connecting electrode 127.
For the TFT 106, the ITO layer 126 is provided for preventing line disconnections and for protecting the underlying layers against etching which is performed on the metal layer 125. The connecting electrode 127 is formed only of the ITO layer 126 in order to raise the aperture ratio and also obtain ohmic contact with the pixel electrode 105.
Then, as shown in FIG. 14E, an area of the n.sup.+ silicon layer 124 corresponding to a channel region in the semiconductor layer 113 is removed, thereby forming the n.sup.+ silicon layers 114 and 115. The interlayer insulative layer 118 is formed on the gate insulative layer 112 so as to cover the elements which are formed on the gate insulative layer 112 except for the area where the terminals 107, 108 and 109 are formed. A transparent conductive layer, for example, an ITO layer is formed on the interlayer insulative layer 118 (FIG. 14E) and on the gate insulative layer 112 so as to cover the connecting portion 130 (FIG. 15E). The ITO layer on the interlayer insulative layer 118 is patterned to form the pixel electrode 105 (FIG. 14E) and also a transparent conductive layer 105a (FIG. 15E).
An alignment layer is formed when necessary. Thus, the active matrix substrate 500 is completed. A liquid crystal display device, for example, is produced by combining the active matrix substrate 500 with a counter substrate (not shown) and injecting a liquid crystal material into the gap between the two substrates and sealing the gap.
According to the active matrix substrate 500 having the above-described structure, the drain electrode 110 which is connected to the pixel electrode 105, the connecting electrode 127 extended from the drain electrode 110, and the connecting portion 130 of the terminals 107 and 108 are formed in the same step as the source signal line 104 including the source electrode 117. However, the connecting electrode 127 and the connecting portion 130 are formed of only the ITO layer 126. Accordingly, the metal layer 125 and the ITO layer 126 need to be separately patterned by photolithography or the like. Thus, the number of production steps is increased, and defective photo-patterning may disadvantageously occur. Consequently, there is an undesirable possibility of source-drain leak. As a result, the production yield is reduced.
In order to reduce the number of steps of performing photolithography so as to raise the production yield even though the aperture ratio is slightly lowered, it is conceivable that the connecting electrode 127, the source signal line 104, and the connecting portion 130 of each of the terminals 107 and 108 are formed of the metal layer 125 and the ITO layer 126.
In such a structure, however, a contact deficiency occurs between the pixel electrode 105 and the connecting electrode 127 and between the transparent conductive layer 105a and the connecting portion 130. Such a contact deficiency occurs because a surface of the metal surface 125 is oxidized by ashing which is performed before the pixel electrode 105 and the transparent conductive layer 105a are formed or by formation of the pixel electrode 105 and the transparent conductive layer 105a.
As a result, the display quality of a display device including the active matrix substrate 500 is significantly reduced. In addition, a signal voltage needs to be raised in order to compensate for the voltage drop which is caused by an increase in the contact resistance. The rise in the signal voltage increases the power consumption.